Generally, a nonvolatile ferroelectric memory device, i.e., a FeRAM (Ferroelectric Random Access Memory) device, processes signal data as fast as DRAM (Dynamic Random Access Memory) and it conserves stored data when power is not supplied so that this memory has been focused on the next generation storage device.
The cell structure of the FeRAM device is similar to that of the DRAM, i.e., the FeRAM device has one switching device (transistor) and one capacitor. Accordingly, the FeRAM device is a memory device having a unit cell of a 1T/1C structure and makes a use of a high remnant polarization of a ferroelectric material in a capacitor. This high remnant polarization contributes the FeRAM device to maintain stored data when an electric field is not applied to the capacitor.
FIG. 1 is a hysteresis loop illustrating characteristics of a nonvolatile ferroelectric memory device.
Referring to FIG. 1, the polarization induced by an electric field is not extinguished even though thereafter the electric field is not applied to the ferroelectric material and this feature is called “remnant polarization” or “spontaneous polarization.” As shown in the hysteresis loop of FIG. 1, an amount of the polarization (d, a) is maintained when the applied voltage is “0”. The nonvolatile ferroelectric memory cell is indicative of a logic value “1” at the state of “d” and is indicative of a logic value “0” at the state of “a.”
A cell array of a nonvolatile ferroelectric memory device and a method for driving such a nonvolatile ferroelectric memory device will be described in detail referring to the accompanying drawings.
FIG. 2A is a schematic view of two unit cells in a conventional split word line structure, FIG. 2B is a circuit diagram for driving the unit cell in FIG. 2A and FIG. 3 is a timing chart illustrating the operation of the circuit in FIG. 2B.
First, referring to FIG. 2A, the unit cell of the split word line structure includes a first split word line SWL1 and a second split word line SWL2 which are extended in the direction of row, a first bit line BL1 and a second bit line BL2 crossing the first and second split word lines SWL1 and SWL2, a first transistor T1 having a gate connected to the first split word line SWL1 and a drain connected to the first bit line BL1, a first ferroelectric capacitor FC1 formed between the second split word line SWL2 and a source of the first transistor T1, a second transistor T2 having a gate connected to the second split word line SWL2 and a drain connected to the second bit line BL2, and a second ferroelectric capacitor FC2 formed between the first split word line SWL1 and a source of the first transistor T2.
A cell array is composed a plurality of unit cells mentioned above. In FIG. 2A, the unit cell makes up of a pair of split word lines SWL1 and SWL2, one bit line BL1, one transistor T1 and one ferroelectric capacitor FC1 in the meaning of data storage; however, the unit cell can be taken by a pair of split word lines SWL1 and SWL2, two bit lines BL1 and BL2, two transistors T1 and T2 and two ferroelectric capacitors FC1 and FC2 in the meaning of structure.
The operation of the unit cell of the split word line structure will be describe below in detail referring to the FIG. 2B.
As shown in FIG. 2B, a plurality of split word line pairs, which has the first and second split word lines SWL1 and SWL2 respectively, are formed in a direction of row and a plurality of bit lines cross the split word pairs lines in a direction of column. As a result, in case where there are n cells (T1/1C) in a direction of row, n+1 bit lines are required to read out data from the unit cell. A sense amplifier for sensing a voltage difference between the first and second bit lines and amplifying the voltage difference are provided and two output nodes of the sense amplifier are respectively connected to a data bus line DL and a data bus bar line /DL.
At this time, a sensing enable signal SEN enables the sense amplifier to amplify the voltage difference and the amplified voltage difference signal from the sense amplifier is transmitted to the dada bus lines DL and /DL in response to a column selection signal CS which is applied to a switching transistor.
The operation of the nonvolatile ferroelectric memory device will be descried referring to FIG. 3 showing a timing chart of the circuit in FIG. 2B.
As illustrated in FIG. 3, at time t0, a chip enable signal /CE (in a low level at the time of activation) is activated to a low level when a bit line equalizing signal EQ is in a high level and the first and second split word lines SWL1 and SWL2 are in a low level. At this time, the bit lines SL1 and BL2 are precharged and the voltage level of the precharge generally set up to a threshold voltage of an NMOS transistor.
At time t1, the bit line equalizing signal EQ is in a low level for data sensing operation and the first and second split word lines SWL1 and SWL2 are activated to a high level. Data stored in the ferroelectric capacitor are transferred to the bit lines BL1 and BL2 according to the activation of the first and second split word lines SWL1 and SWL2. When logic data “1(high level voltage)” is sorted in the ferroelectric capacitor, a voltage level on the bit line BL1 is highly increased because the point “d” is moved to the point “f” in FIG. 1 with the charge sharing between the bit line BL1 and the ferroelectric capacitor. However, when logic data “0 (low level voltage)” is sorted in the ferroelectric capacitor, a voltage level on the bit line BL1 is increased a little because the point “a” is moved to the point “f” in FIG. 1 with the charge sharing between the bit line BL1 and the ferroelectric capacitor.
At time t2, the sense amplifier is enabled in response to the sense amplifier enable signal SEN after the cell data are transferred to the bit lines BL1 and BL2 and the first and second split word lines SWL1 and SWL2 are activated.
On the other hand, since the logic data “1” can not be restored at a state that the first and second split word lines SWL1 and SWL2 are in a high level, data restoration should be achieved at time t3. At time t3, the column selection signal CS is activated to a high voltage level and the bit lines are electrically connected to the data bus lines. Data on the bit lines are transferred to the data bus lines at a read operation and data on the data bus lines are transferred to the bit lines are a write operation. Also, at time t3, the first split word line SWL1 is transited to a low level but the second split word line SWL2 keeps the voltage level low, thereby turning on the second transistor T2. At this time, in case where the second bit line BL2 is in a high level, a voltage level corresponding to the high level on the bit line BL2 is transferred to one of terminals of the second ferroelectric capacitor FC2. The other the other of terminals of the second ferroelectric capacitor FC2 is electrically connected to the first split word line SWL1 with a low level. Accordingly, the logic data “1” is restored.
At time t4, in case where logic data “0” are on the first bit line BL1 or the second bit line BL2, i.e., logic data “0” write operation, the first split word line SWL1 is transited to a high level and then the logic data “0” is written in the first ferroelectric capacitor FC1. However, in case where the first and second bit lines BL1 and BL3 are in a high level, there is no change of cell data.
Also, at time t5, the first split word line SWL1 is in a high level but the second split word line SWL2 transited to a low level, thereby turning on the first transistor T1. At this time, in case where the first bit line BL1 is in a high level, a voltage level corresponding to the high level on the bit line BL2 is transferred to one of terminals of the first ferroelectric capacitor FC1. The other the other of terminals of the first ferroelectric capacitor FC1 is electrically connected to the second split word line SWL2 with a low level. Accordingly, the logic data “1” is restored.
Finally, at time t6, the equalizing signal is activated to a high level so that charge sharing is achieved between the first and second bit lines BL1 and BL2 for the next operation.
As mentioned above, the conventional ferroelectric memory device has a split word line structure to decrease a load on a plate line; however, this has limitations on a chip size, especially in a cell array and a driving circuit of cells.